FPGA 130nm Characterization Chip

FPGA interconnect traditionally dominates energy and delay, and designs such as low-swing interconnect have been proven to reduce the interconnect burden for low energy FPGAs. This paper presents an optimized low-swing interconnect for FPGAs operating in the sub-threshold region. We also address signal degradation along lengthy interconnect paths and examine strategies for inserting low-switching-threshold repeaters. A 130nm test chip implementing low-swing interconnect meshes with different circuit parameters is measured. The results show that optimization of the low-swing interconnect provides up to 60.2% lower energy-delay-product (EDP) than a straightforward, un-optimized low-swing design at VDD = 0.4V. Furthermore, the simulation results show that the optimized lowswing interconnect is 97.7% faster and 42.7% lower energy than a traditional uni-directional interconnect at VDD = 0.4V.

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ChipLayout.PNG2.11 MB