Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool

TitleDesign Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool
Publication TypeConference Paper
Year of Publication2016
AuthorsLiu, N., and B. H. Calhoun
Conference NameIEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Citation Key391
AttachmentSize
ISVLSI-2016_Poster_ViPro.pdf566.28 KB