A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems

TitleA 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems
Publication TypeConference Paper
Year of Publication2015
AuthorsLukas, C. J., and B. H. Calhoun
Conference NameInternational Symposium on Circuits and Systems (ISCAS)
Date Published05/2015
Conference LocationLisbon
URLhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7169283
Citation Key354
Full Text

As energy-constrained systems continue to reduce
their power consumption, finding an optimal point of operation
for the principle components in the energy budget becomes
increasingly important. With energy dominant system
components like communication circuits, it is important to
consider both energy-per-bit and power in the context of the
system’s use cases. In this paper, we propose optimization of
chip-to-chip links considering both energy-per-cycle and energyper-bit
to find the optimal operating voltage and activity factor
while minimizing wasted energy and power. A fabricated 130 nm
chip was used to verify this finding and resulted in an energyper-bit
of 0.38 pJ/bit and power of 1.24 nW.

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