Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

TitleAnalyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN
Publication TypeJournal Article
Year of Publication2012
AuthorsBoley, J., J. Wang, and B. H. Calhoun
JournalJournal of Low Power Electronics and Applications (JLPEA)
Volume2
Start Page143
Issue2
Pagination12
Date Published04/2012
Citation Key339