A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node

TitleA 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node
Publication TypeConference Paper
Year of Publication2013
AuthorsShrivastava, A., J. Pandey, B. Otis, and B. H. Calhoun
Conference NameVLSI Design Conference
Date Published01/2013
Citation Key298
AttachmentSize
2013_Shrivastava_VLSIDesign.pdf477.58 KB
2013_Shrivastava_VLSIDesign_Slides.pdf912.17 KB