SRAM Design Automation

ViPro for Register Files (RFs) - not only explores methodologies of designing low power and high performance RFs and it also extends a virtual prototyping (ViPro) tool to support fast and efficient estimation of different design knobs on the overall multi-port RF macros. The extension of ViPro fills the blank of the multi-port register files, and provides hierarchical BL scheme as an extra knob for better memory design.

Similar tool likes CACTI developed by HP Laboratories also evaluates delay and energy of memories, but the results are extremely inaccurate due to using a mathematical circuit model. The left figure above illustrates the delay and energy of a gate chain which is a fundamental element of circuits, and results of CACTI using high performance and low power transistors are both substantially different from SPICE simulation results of the commercial technology and the predictive technology model for the same gate chain.

The right figure above shows the Pareto curves of the 8T 1R/1W bitcell with single-ended BL sensing, differential BL sensing, and two hierarchical BL (16bits/LBL & 32bits/LBL) sensing schemes at 8KB capacity. Two hierarchical BL sensing schemes contribute to the combined Pareto curve.

Virtual Prototyper (ViPro) - enables iterative SRAM design space exploration to facilitate optimal, sub-45nm SRAM designs. SRAM component circuits (e.g. decoder, SA etc.) are characterized in terms of energy and delay. This data is plugged into an SRAM model to generate an optimal, base-case SRAM prototype for any technology. Through an iterative process that involves designer inputs, ViPro helps the designer to zero in on an optimal SRAM design.

Technology Agnostic Simulation Environment (TASE) - uses parametrized simulation templates for ease of circuit (spectre) simulation across technology nodes. Using a single TASE template for each sim, SRAM designers can run groups of sims for any technology node, simply by changing a configuration file that contains all the technology-specific information. TASE is also used by ViPro for Energy-Delay characterization of SRAM component circuits. You can download TASE here

One important aspect of SRAM design, which we are building into these tools, is the statistical analysis of SRAM behavior in the presence of variations. We investigate methods for rapidly and accurately assessing variation impact.

Faculty:
Ben Calhoun

Students:
Arijit Banerjee, Harsh Patel, Ningxi Liu

Tool Publications:
Liu, N., and B. H. Calhoun, "Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.

Boley, J., P. Beshay, and B. H. Calhoun, "Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization", Transactions of Very Large Scale Integration Systems, 2015.

Boley, J., P. Beshay, and B. Calhoun, "Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization", SRC TECHCON, 09/2013.

Nalam, S., M. Bhargava, K. Ringgenberg, K. Mai, and B. H. Calhoun, "A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes", ICCD, pp. 523-528, 2009.

Bhargava, M., S. Nalam, B. H. Calhoun, and K. Mai, "An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization", TECHCON, 2009.

Nalam, S., M. Bhargava, K. Mai, and B. H. Calhoun, "Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers", Design Automation Conference (DAC), pp. 138-143, 06/2010.

Modeling Publications:
Boley, J., V. Chandra, R. Aitken, and B. H. Calhoun, "Modeling SRAM Dynamic VMIN", International Conference on IC Design and Technology (ICICDT), 06/2014.

Ryan, J. F., S. Khanna, and B. H. Calhoun, "An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal", Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.

Wang, J., and B. H. Calhoun, "Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations", Transactions on VLSI Systems (TVLSI), 2011.