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Panoptic Dynamic Voltage Scaling (PDVS)
Panoptic Dynamic Voltage Scaling (PDVS) is an exciting approach to ultra low power (ULP) design to reduce energy without sacrificing performance. The objective of PDVS is to dynamically scale energy of a digital circuit to meet real-time energy constraints and thus extend battery life. Consumers demand longer battery life. Some batteries in remote sensors such a forest or desert cannot be changed. Changing batteries within biomedical devices could have adverse effects on the patient.
Like Universal Dynamic Voltage Scaling (UDVS), PDVS exploits timing slack the voltage is reduced to the minimum voltage possible to complete the instruction to reduce the energy. Unlike UDVS, PDVS focuses on a fine-grained implementation by placing headers attached to different voltages on individual blocks, such as adders and multipliers, and allowing headers to dither between voltages (Figure above). Adding headers to the circuit allows multiple levels of energies and thus maximize energy savings per data flow graph at a minimum cost as seen in the die photo. Execution schedules optimized for different modes of operation are calculated in advance currently. Through PDVS we expect greater energy savings than other DVS schemes due to energy savings from dithering as well as being able to better exploit timing slack in data flow graphs. In this topology, the circuit will able to switch into a sub-threshold mode for additional energy savings. Applications for PDVS include but are not limited to battery-constrained sensors and processors.
John Lach, Ben Calhoun
Yousef Shakhsheer, Kyle Craig, Sudhanshu Khanna, Saad Arrabi
"REESES: Rapid Efficient Energy Scalable ElectronicS", GOMAC Tech, 03/2010.
"Flexible Circuits and Architectures for Ultra Low Power", Proceedings of the IEEE, vol. 98, pp. 267-282, 02/2010.
"Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling", International Conference on Computer Design, pages 605-611, 08/2008.
"Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design", International Conference on Computer Design (ICCD), pp. 491-497, 01/10/2009.