Circuit Techniques for Lowering SRAM VMIN

We investigate the application of these peripheral assist methods to reduce the operating voltage of SRAM, called VMIN. Lowering VMIN helps to decrease power consumption and also keeps pace with the dropping logic VDD, allowing for easier integration. Large scale 6T SRAM beyond 65nm will increasingly rely on assist methods to overcome the functional limitations associated with scaling and the inherent read stability/write margin trade off.

The primary focus of the circuit assist methods has been improved read or write margin with less attention given to the the implications for performance. Margin sensitivity and margin/delay analysis tools are introduced for assessing the functional effectiveness of the bias based assist methods and show the direct implications on voltage sensitive yield. A margin/delay analysis of bias based circuit assist methods is developed, highlighting the assist impact on the functional metrics, margin and performance.

Assist methods are often used in conjunction with other techniques. For example, we investigate different schemes for improving sense amplifier performance in the presence of variation.

In the extreme case, we also apply circuit assists (along with alternative bitcells) to support sub-threshold operation of memories. These memories can function down to 0.3V or lower, which is essential for severely energy constrained applications like Body Sensor Networks.

Harsh Patel, Ningxi Liu, Arijit Banerjee


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Beshay, P., J. Bolus, T. Blalock, V. Chandra, and B. H. Calhoun, "SRAM Sense Amplifier Offset Cancellation Using BTI Stress", Subthreshold Microelectronics Conference, 10/2012.

Boley, J., J. Wang, and B. H. Calhoun, "Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin", Journal of Low Power Electronics and Applications, 04/2012.

Ryan, J. F., S. Khanna, and B. H. Calhoun, "An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal", Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.

Wang, J., and B. H. Calhoun, "Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations", Transactions on VLSI Systems (TVLSI), 2011.

R. W.Mann, S. Nalam, W. C. J. B. H., "Limits of Bias Based Assist Methods in Nano-Scale 6T SRAM", ISQED, pp. 1-8, 2010.

Mann, R. W., J. Wang, S. Nalam, S. Khanna, G. Braceras, H. Pilo, and B. H. Calhoun, "Impact of circuit assist methods on margin and performance in 6T SRAM", Journal of Solid State Electronics, vol. 54: Elsevier, pp. 1398-1407, 11/2010.