Energy Efficient Circuit Design

Panoptic Dynamic Voltage Scaling (PDVS)

Panoptic Dynamic Voltage Scaling (PDVS) is an exciting approach to ultra low power (ULP) design to reduce energy without sacrificing performance. The objective of PDVS is to dynamically scale energy of a digital circuit to meet real-time energy constraints and thus extend battery life. Consumers demand longer battery life. Some batteries in remote sensors such a forest or desert cannot be changed. Changing batteries within biomedical devices could have adverse effects on the patient.

Sub-Threshold FPGAs

Ultra low power (ULP) miniature devices are enabling a new generation of applications for areas such as healthcare and wireless environmental control. Reconfigurable circuits, designed for low-power operation, promise to make ubiquitous implementation of these systems possible by providing a combination of adequate computing capability, flexibility, and low cost.

Advanced Power distribution methods and their effects on the on-chip power network

Aggressive scaling according to Moore’s Law, combined with the push to incorporate more functionality and higher performance on a single chip, has created the widely known power problem in modern ICs. Power consumption has become a major limiting factor in many designs. A number of solutions have been preliminarily explored to help improve the energy efficiency of chips, including clock gating, power gating, local voltage regulation, and dynamic voltage scaling. While theoretical benefits of these techniques are known, their full impact on the overall power distribution network remains uncertain. This project aims to address the impact of Panoptic Dynamic Voltage Scaling (PDVS) on the power distribution network and compare them against alternative low power techniques.

Implementable Privacy and Security for RFIDs

This project explores algorithm, architectural and circuit ideas for implementation of Security Functions on RFID tags. An RFID tag harvests its power from the RF field that a reader sets-up while reading the tag. Typical power consumption, gate count and cost are below 10uW, 50K and 10 cents respectively. We explore energy efficient sub-threshold logic and memory design that can operate at sub-10uW power levels, while also delivering performance required for computationally intensive encryption algorithms.

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