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"Design Principles for Digital CMOS Integrated Circuit Design", The Modular Series of Microelectronic Device & Circuit Design, eds. C. Sodini and R. Howe: NTS Press, 03/2012.
Sub-threshold Design for Ultra Low-Power Systems, : Springer, 2006.
"Low Energy Digital Circuit Design", AmIware: Hardware Drivers of Ambient Intelligence: Springer, 2006.
"Optimizing Power @ Design Time – Memory", Low Power Design Essentials, 2009.
"Optimizing Power @ Standby – Memory", Low Power Design Essentials, 2009.
"Power Gating and Dynamic Voltage Scaling", Leakage in Nanometer Technologies: Springer, pp. 41-75, 2006.
"Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs", Solid State Circuits Technologies: INTECH, 2010.
"A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems", International Symposium on Circuits and Systems (ISCAS), Lisbon, 05/2015.
"A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications", Symposium on VLSI Circuits, 2013.
"A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications", International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, IEEE, 2016.
"A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting", IEEE Custom Integrated Circuits Conference (CICC), 2014.
"A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations", Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, 09/2015.
"A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.
"A 150nW, 5ppm/oC, 100kHz On-Chip Clock Source for Ultra Low Power SoCs", Custom Integrated Circuits Conference, San Jose, IEEE, 09/2012.
"A 2.6-μW Sub-threshold Mixed-signal ECG SoC", Symposium on VLSI Circuits, 6/15/2009.
"A 23 nW CMOS ultra-Low Power Temperature Sensor Operational from 0.2 V", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Rohnert Park, CA, IEEE, 10/2015.
"A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS", IEEE International Solid-State Circuits Conference (ISSCC), 2016.
A 256kb Sub-threshold SRAM in 65nm CMOS, , IEEE International Solid-State Circuits Conference, pp. 628-629, 02/2006.
"A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systems", EEE International Solid-State Circuits Conference (ISSCC), 2015.
"A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node", VLSI Design Conference, 01/2013.
"A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic", European Solid State Circuits Conference (ESSCIRC), 2016.
"A 6.45 μW Self-Powered IoT SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios", ISSCC, San Francisco, CA, IEEE, 02/2015.
"A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V", Custom Integrated Circuits Conference, San Jose, 09/2011.
"An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal", Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.