Publications

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Book
Calhoun, B. H., "Design Principles for Digital CMOS Integrated Circuit Design", The Modular Series of Microelectronic Device & Circuit Design, eds. C. Sodini and R. Howe: NTS Press, 03/2012.
Book Chapter
Calhoun, B. H., C. Schurgers, A. Wang, and A. Chandrakasan, "Low Energy Digital Circuit Design", AmIware: Hardware Drivers of Ambient Intelligence: Springer, 2006.
Calhoun, B. H., James Kao, and A. Chandrakasan, "Power Gating and Dynamic Voltage Scaling", Leakage in Nanometer Technologies: Springer, pp. 41-75, 2006.
Wang, J., and B. H. Calhoun, "Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs", Solid State Circuits Technologies: INTECH, 2010.  Download: 2010_Wang_INTECH.pdf (763.49 KB)
Conference Paper
Lukas, C. J., and B. H. Calhoun, "A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems", International Symposium on Circuits and Systems (ISCAS), Lisbon, 05/2015.  Download: 2015_Lukas_ISCAS.pdf (616.96 KB)
Roy, A., P. Grossmann, S. Vitale, and B. Calhoun, "A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications", International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, IEEE, 2016.  Download: ISQED2016_MSP430_MITLL.pdf (2.16 MB); ISQED_Poster_final.pdf (531.22 KB)
Huang, Y., A. Shrivastava, and B. H. Calhoun, "A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.
Shrivastava, A., and B. H. Calhoun, "A 150nW, 5ppm/oC, 100kHz On-Chip Clock Source for Ultra Low Power SoCs", Custom Integrated Circuits Conference, San Jose, IEEE, 09/2012.  Download: M-01.pdf (874.13 KB)
Akella, D., A. Shrivastava, and B. H. Calhoun, "A 23 nW CMOS ultra-Low Power Temperature Sensor Operational from 0.2 V", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Rohnert Park, CA, IEEE, 10/2015.  Download: A 23 nW CMOS ultra-Low Power Temperature Sensor Operational from 0.2 V.pdf (1.47 MB)
Calhoun, B. H., and A. Chandrakasan, A 256kb Sub-threshold SRAM in 65nm CMOS, , IEEE International Solid-State Circuits Conference, pp. 628-629, 02/2006.  Download: 2006_Calhoun_ISSCC.pdf (528.34 KB); 2006_Calhoun_ISSCC_Slides.pdf (410.77 KB)