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"A 23 nW CMOS ultra-Low Power Temperature Sensor Operational from 0.2 V", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Rohnert Park, CA, IEEE, 10/2015.
"A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications", Journal of Low Power Electronics and Applications (JLPEA), vol. 6, issue 2, 2016.
"Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems", International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.
"Using island-style bi-directional intra-CLB routing in low-power FPGAs", 25th International Conference on Field Programmable Logic and Applications (FPL), 09/2015.
"A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs", International Symposium on Quality Electronic Design (ISQED), 02,2014.
"A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations", Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, 09/2015.
"An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications", Journal of Low Power Electronics and Applications (JLPEA), vol. 4, issue 2, pp. 19, 05,2014.
"An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell", S3S, Monterey, CA, 2013.
"SRAM Sense Amplifier Offset Cancellation Using BTI Stress", Subthreshold Microelectronics Conference, 10/2012.
"Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM", Design Automation Conference (DAC), 2014.
"Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry", Subthreshold Microelectronics Conference, 10/2012.
"A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers", Journal of Low Power Electronics and Applications, 05/2013.
"Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin", Journal of Low Power Electronics and Applications, 04/2012.
"Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization", SRC TECHCON, 09/2013.
"Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset", International Symposium on Quality Electronic Design, 03/2015.
"Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization", Transactions of Very Large Scale Integration Systems, 2015.
"Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN", Design Automation and Test Europe, 03/2013.
"Modeling SRAM Dynamic VMIN", International Conference on IC Design and Technology (ICICDT), 06/2014.
"Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN", Journal of Low Power Electronics and Applications (JLPEA), vol. 2, issue 2, pp. 12, 04/2012.
"What is a Body Sensor Network?", ACM / SIGDA Newsletter, vol. 41, issue 10, 10/2011.
A 256kb Sub-threshold SRAM in 65nm CMOS, , IEEE International Solid-State Circuits Conference, pp. 628-629, 02/2006.
"A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation", IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 03/2007.