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Banerjee, A., and B. H. Calhoun, "An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications", Journal of Low Power Electronics and Applications (JLPEA), vol. 4, issue 2, pp. 19, 05,2014.
Boley, J., V. Chandra, R. Aitken, and B. H. Calhoun, "Modeling SRAM Dynamic VMIN", International Conference on IC Design and Technology (ICICDT), 06/2014.
Boley, J., J. Wang, and B. H. Calhoun, "Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN", Journal of Low Power Electronics and Applications (JLPEA), vol. 2, issue 2, pp. 12, 04/2012.
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Calhoun, B. H., and A. Chandrakasan, "A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation", IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 03/2007.  Download: 2007_Calhoun_JSSC.pdf (1.79 MB)
Calhoun, B. H., and A. Chandrakasan, "Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS", IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 07/2006.  Download: 2006_Calhoun_JSSC.pdf (660.21 KB)