Publications

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2006
Calhoun, B. H., and A. Chandrakasan, A 256kb Sub-threshold SRAM in 65nm CMOS, , IEEE International Solid-State Circuits Conference, pp. 628-629, 02/2006.  Download: 2006_Calhoun_ISSCC.pdf (528.34 KB); 2006_Calhoun_ISSCC_Slides.pdf (410.77 KB)
Calhoun, B. H., and A. Chandrakasan, "Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering", IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 01/2006.  Download: 2006_Calhoun_JSSC.pdf (1.05 MB)
Calhoun, B. H., C. Schurgers, A. Wang, and A. Chandrakasan, "Low Energy Digital Circuit Design", AmIware: Hardware Drivers of Ambient Intelligence: Springer, 2006.
Calhoun, B. H., James Kao, and A. Chandrakasan, "Power Gating and Dynamic Voltage Scaling", Leakage in Nanometer Technologies: Springer, pp. 41-75, 2006.
2005
2004
Calhoun, B. H., A. Wang, and A. Chandrakasan, "Device Sizing for Minimum Energy Operation in Subthreshold Circuits", Custom Integrated Circuits Conference (CICC), pp. 95-98, 10/2004.  Download: 2004_Calhoun_CICC.pdf (182.83 KB)
Calhoun, B. H., and A. Chandrakasan, "Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures", IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 09/2004.  Download: 2004_Calhoun_JSSC.pdf (459.01 KB)
Calhoun, B. H., and A. Chandrakasan, "Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits", International Symposium on Low Power Electronics and Design, pp. 90-95, 08/2004.  Download: 2004_Calhoun_ISLPED.pdf (295.91 KB); 2004_Calhoun_ISLPED_Slides.pdf (579.5 KB)
Calhoun, B. H., F. A. Honore, and A. Chandrakasan, "A Leakage Reduction Methodology for Distributed MTCMOS", IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 05/2004.  Download: 2004_Calhoun_JSSC.pdf (783.26 KB)
2003
Calhoun, B., and A. Chandrakasan, "Standby Voltage Scaling for Reduced Power", Custom Integrated Circuits Conference (CICC), pp. 639-642, 09/2003.  Download: 2003_Calhoun_CICC.pdf (108.73 KB)
Calhoun, B. H., F. A. Honore, and A. Chandrakasan, "Design Methodology for Fine-Grained Leakage Control in MTCMOS", International Symposium on Low Power Electronics and Design (ISLPED), pp. 104-109, 08/2003.  Download: 2003_Calhoun_ISLPED.pdf (172.33 KB)
2002
Sotiriadis, P., O. Franza, D. Bailey, B. Calhoun, D. Lin, and A. Chandrakasan, "Fast Algorithm for Clock Grid Simulation", European Solid State Circuits Conference (ESSCIRC), pp. 771-774, 09/2002.  Download: 2002_Callhoun_ESSCIRC.pdf (1018.66 KB)
2001