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Hanson, M. A., H. C. Powell Jr, A. T. Barth, K. Ringgenberg, B. H. Calhoun, J. H. Aylor, and J. Lach, "Body Area Sensor Networks: Challenges and Opportunities", Computer, vol. 42, no. 1: IEEE Computer Society Press Los Alamitos, CA, USA, pp. 58–65, 1/2009.  Download: 2009_Hanson_Computer.pdf (2.62 MB)
Wang, J., and B. H. Calhoun, "Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond", IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 11/2008.  Download: 2008_Wang_JSSC.pdf (579 KB)
Wang, J., S. Nalam, and B. H. Calhoun, "Analyzing Static and Dynamic Write Margin for Nanometer SRAMs", International Symposium on Low Power Electronics and Design, pp. 129-134, 08/2008.  Download: 2008_Wang_ISLPED.pdf (582.96 KB); 2008_Wang_ISLPED_Slides.pdf (703.11 KB)
Di, L., M. Putic, J. Lach, and B. H. Calhoun, "Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling", International Conference on Computer Design, pages 605-611, 08/2008.  Download: 2008_Di_ICCD.pdf (319.64 KB)
Ryan, J. F., and B. H. Calhoun, "Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation", International Symposium on Quality Electronic Design, pp. 127-132, 03/2008.  Download: 2008_Ryan_ISQED_Slides.pdf (177.05 KB); 2008_Ryan_ISQED.pdf (362.75 KB)
Calhoun, B. H., X. L. Yu Cao, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, "Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS", Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore's Law), vol. 96, pp. 343-365, 02/2008.  Download: 2008_Calhoun_IEEEProceedings.pdf (1.22 MB)
Calhoun, B. H., A. Wang, N. Verma, and A. Chandrakasan, "Sub-threshold Design: The Challenges of Minimizing Circuit Energy", International Symposium on Low Power Electronics and Design (ISLPED), pp. 366-368, 10/2006.  Download: 2006_Calhoun_ISLPED.pdf (2.66 MB); 2006_Calhoun_ISLPED_Slides.pdf (897.35 KB)