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"Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM", Design Automation and Test Europe (DATE), 03/2011.
"Impact of circuit assist methods on margin and performance in 6T SRAM", Journal of Solid State Electronics, vol. 54: Elsevier, pp. 1398-1407, 11/2010.
"Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers", Design Automation Conference (DAC), pp. 138-143, 06/2010.
"Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation", ISQED, pp. 139-146, 2010.
"Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T", CICC, pp. 709-712, 2009.
"A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes", ICCD, pp. 523-528, 2009.