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Wang, J., S. Nalam, and B. H. Calhoun, "Analyzing Static and Dynamic Write Margin for Nanometer SRAMs", International Symposium on Low Power Electronics and Design, pp. 129-134, 08/2008.  Download: 2008_Wang_ISLPED.pdf (582.96 KB); 2008_Wang_ISLPED_Slides.pdf (703.11 KB)
Mann, R. W., J. Wang, S. Nalam, S. Khanna, G. Braceras, H. Pilo, and B. H. Calhoun, "Impact of circuit assist methods on margin and performance in 6T SRAM", Journal of Solid State Electronics, vol. 54: Elsevier, pp. 1398-1407, 11/2010.  Download: 2010_Mann_SSE.pdf (793.53 KB)
Boley, J., J. Wang, and B. H. Calhoun, "Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN", Journal of Low Power Electronics and Applications (JLPEA), vol. 2, issue 2, pp. 12, 04/2012.