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Akella, D., A. Shrivastava, and B. H. Calhoun, "A 23 nW CMOS ultra-Low Power Temperature Sensor Operational from 0.2 V", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Rohnert Park, CA, IEEE, 10/2015.  Download: A 23 nW CMOS ultra-Low Power Temperature Sensor Operational from 0.2 V.pdf (1.47 MB)
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Calhoun, B. H., "Design Principles for Digital CMOS Integrated Circuit Design", The Modular Series of Microelectronic Device & Circuit Design, eds. C. Sodini and R. Howe: NTS Press, 03/2012.
Calhoun, B. H., and A. Chandrakasan, A 256kb Sub-threshold SRAM in 65nm CMOS, , IEEE International Solid-State Circuits Conference, pp. 628-629, 02/2006.  Download: 2006_Calhoun_ISSCC.pdf (528.34 KB); 2006_Calhoun_ISSCC_Slides.pdf (410.77 KB)
Calhoun, B. H., and A. Chandrakasan, "Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering", IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 01/2006.  Download: 2006_Calhoun_JSSC.pdf (1.05 MB)
Calhoun, B. H., F. A. Honore, and A. Chandrakasan, "Design Methodology for Fine-Grained Leakage Control in MTCMOS", International Symposium on Low Power Electronics and Design (ISLPED), pp. 104-109, 08/2003.  Download: 2003_Calhoun_ISLPED.pdf (172.33 KB)
Calhoun, B. H., X. L. Yu Cao, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, "Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS", Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore's Law), vol. 96, pp. 343-365, 02/2008.  Download: 2008_Calhoun_IEEEProceedings.pdf (1.22 MB)
Calhoun, B. H., A. Wang, and A. Chandrakasan, "Device Sizing for Minimum Energy Operation in Subthreshold Circuits", Custom Integrated Circuits Conference (CICC), pp. 95-98, 10/2004.  Download: 2004_Calhoun_CICC.pdf (182.83 KB)
Calhoun, B. H., and A. Chandrakasan, "Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures", IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 09/2004.  Download: 2004_Calhoun_JSSC.pdf (459.01 KB)
Calhoun, B. H., and A. Chandrakasan, "A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation", IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 03/2007.  Download: 2007_Calhoun_JSSC.pdf (1.79 MB)
Calhoun, B. H., A. Wang, and A. Chandrakasan, "Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits", IEEE Journal of Solid-State Circuits (JSSC), vol. 40, pp. 1778-1786, 09/2005.  Download: 2005_Calhoun_JSSC.pdf (761.2 KB)
Calhoun, B. H., S. Khanna, Y. Zhang, J. Ryan, and B. Otis, "System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms", International Symposium on Circuits and Systems (ISCAS), Paris, France, pp. 269-272, 05/2010.  Download: 2010_Calhoun_ISCAS.pdf (537.44 KB)