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Wooters, S. N., B. H. Calhoun, and T. N. Blalock, "An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS", IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 04/2010.  Download: 2010_Wooters_TCASII.pdf (565.79 KB)
Wang, J., and B. H. Calhoun, "Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs", Solid State Circuits Technologies: INTECH, 2010.  Download: 2010_Wang_INTECH.pdf (763.49 KB)
Khanna, S., and B. H. Calhoun, "Serial Sub-threshold Circuits for Ultra-Low-Power Systems", International Symposium on Low Power Electronics and Design, 8/19/2009.  Download: 2009_Khanna_ISLPED.pdf (139.21 KB); 2009_Khanna_ISLPED_Slides.pdf (426.32 KB)
Wang, J., and B. H. Calhoun, "Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond", IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 11/2008.  Download: 2008_Wang_JSSC.pdf (579 KB)
Di, L., M. Putic, J. Lach, and B. H. Calhoun, "Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling", International Conference on Computer Design, pages 605-611, 08/2008.  Download: 2008_Di_ICCD.pdf (319.64 KB)
Ryan, J. F., and B. H. Calhoun, "Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation", International Symposium on Quality Electronic Design, pp. 127-132, 03/2008.  Download: 2008_Ryan_ISQED_Slides.pdf (177.05 KB); 2008_Ryan_ISQED.pdf (362.75 KB)
Calhoun, B. H., X. L. Yu Cao, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, "Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS", Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore's Law), vol. 96, pp. 343-365, 02/2008.  Download: 2008_Calhoun_IEEEProceedings.pdf (1.22 MB)
Calhoun, B. H., A. Wang, N. Verma, and A. Chandrakasan, "Sub-threshold Design: The Challenges of Minimizing Circuit Energy", International Symposium on Low Power Electronics and Design (ISLPED), pp. 366-368, 10/2006.  Download: 2006_Calhoun_ISLPED.pdf (2.66 MB); 2006_Calhoun_ISLPED_Slides.pdf (897.35 KB)
Calhoun, B. H., and A. Chandrakasan, "Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS", IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 07/2006.  Download: 2006_Calhoun_JSSC.pdf (660.21 KB)