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Klinefelter, A., Y. Zhang, B. Otis, and B. H. Calhoun, "A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC", Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, issue 12, pp. 941, 12/2012.  Download: 2012_Klinefelter_CircuitsSystems.pdf (858.86 KB)
Shrivastava, A., and B. H. Calhoun, "A 150nW, 5ppm/oC, 100kHz On-Chip Clock Source for Ultra Low Power SoCs", Custom Integrated Circuits Conference, San Jose, IEEE, 09/2012.  Download: M-01.pdf (874.13 KB)
Calhoun, B. H., "Design Principles for Digital CMOS Integrated Circuit Design", The Modular Series of Microelectronic Device & Circuit Design, eds. C. Sodini and R. Howe: NTS Press, 03/2012.
Ryan, J. F., and B. H. Calhoun, "A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS", Custom Integrated Circuits Conference (CICC), 20/09/2010.  Download: 2010_Ryan_CICC.pdf (808.71 KB)
Wang, J., A. Singhee, R. A. Rutenbar, and B. H. Calhoun, "Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs", Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, issue 12, pp. 1908-1920, 12/2010.  Download: 2010_Wang_TCAD.pdf (1.4 MB)
Qi, J., J. Wang, B. H. Calhoun, and M. Stan, "SRAM-Based NBTI/PBTI Sensor System Design", Design Automation Conference (DAC), San Diego, CA, pp. 849-852, 06/2010.  Download: 2010_Qi_DAC.pdf (421.5 KB)
Calhoun, B. H., S. Khanna, Y. Zhang, J. Ryan, and B. Otis, "System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms", International Symposium on Circuits and Systems (ISCAS), Paris, France, pp. 269-272, 05/2010.  Download: 2010_Calhoun_ISCAS.pdf (537.44 KB)