Publications

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Filters: Author is Joseph F. Ryan  [Clear All Filters]
2013
2012
2010
Ryan, J. F., and B. H. Calhoun, "A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS", Custom Integrated Circuits Conference (CICC), 20/09/2010.  Download: 2010_Ryan_CICC.pdf (808.71 KB)
2008
Ryan, J. F., and B. H. Calhoun, "Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation", International Symposium on Quality Electronic Design, pp. 127-132, 03/2008.  Download: 2008_Ryan_ISQED_Slides.pdf (177.05 KB); 2008_Ryan_ISQED.pdf (362.75 KB)
2007