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Filters: Author is Boley, J. [Clear All Filters]
"A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs", J. Low Power Electron. Appl. (JLPEA), vol. 6, issue 2, 2016.
"Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset", International Symposium on Quality Electronic Design, 03/2015.
"Modeling SRAM Dynamic VMIN", International Conference on IC Design and Technology (ICICDT), 06/2014.
"Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN", Journal of Low Power Electronics and Applications (JLPEA), vol. 2, issue 2, pp. 12, 04/2012.