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Filters: Author is Jiajing Wang [Clear All Filters]
"Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin", Journal of Low Power Electronics and Applications, 04/2012.
"An Enhanced Canary-based System with BIST for SRAM Standby Power Reduction", Transactions on VLSI Systems (TVLSI), 2011.
"Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs", Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, issue 12, pp. 1908-1920, 12/2010.
"Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress", CICC, San Jose, CA, 09/2010.
"SRAM-Based NBTI/PBTI Sensor System Design", Design Automation Conference (DAC), San Diego, CA, pp. 849-852, 06/2010.
"Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs", Solid State Circuits Technologies: INTECH, 2010.
"Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond", IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 11/2008.
"An Enhanced Adaptive Canary System for SRAM Standby Power Reduction", TECHCON, 09/2008.
"Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design", International Conference on VLSI Design, India, pp. 131-136, 00/01/2008.
"Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM", Custom Integrated Circuits Conference (CICC), pp. 29-32, 00/09/2007.
"Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array", European Solid State Circuits Conference (ESSCIRC), pp. 400-403, 00/09/2007.
"Analyzing and Modeling Process Balance for Sub-threshold Circuit Design", GLSVLSI, pp. 275-280, 00/03/2007.