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In Press
J.Bolus, B. H. Calhoun, and T.Blalock, "39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation", Journal of Low Power Electronics and Applications (JLPEA), vol. 4, issue 3, pp. 16, 09/2014, In Press.
Yahya, F. B., H. N. Patel, V. Chandra, and B. H. Calhoun, "Combining SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation", 6th Asia Symposium on Quality Electronic Design (ASQED 2015), Kuala Lumpur, Malaysia, 08/2015.  Download: asQED2015_Yahya_Rev5.pdf (223.24 KB); asQED2015_Yahya_Pres_Rev1.pdf (1.29 MB)
Lukas, C. J., and B. H. Calhoun, "A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems", International Symposium on Circuits and Systems (ISCAS), Lisbon, 05/2015.  Download: 2015_Lukas_ISCAS.pdf (616.96 KB)
Arrabi, S., D. Moore, L. Wang, K. Skadron, and B. H. Calhoun, "Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems", International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.  Download: 2014_Arrabi_FCCM.pdf (225.48 KB)
Boley, J., V. Chandra, R. Aitken, and B. H. Calhoun, "Modeling SRAM Dynamic VMIN", International Conference on IC Design and Technology (ICICDT), 06/2014.
Banerjee, A., and B. H. Calhoun, "An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications", Journal of Low Power Electronics and Applications (JLPEA), vol. 4, issue 2, pp. 19, 05,2014.