- Chip Gallery
- Photo Gallery
"A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting", IEEE Custom Integrated Circuits Conference (CICC), 2014, In Press.
"39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation", Journal of Low Power Electronics and Applications (JLPEA), vol. 4, issue 3, pp. 16, 09/2014, In Press.
"A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM", ISLPED, 08/2014, In Press.
"Modeling SRAM Dynamic VMIN", International Conference on IC Design and Technology (ICICDT), 06/2014, In Press.
"A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems", ISCAS, Lisbon, 05/2015.
"Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications", International Symposium on Circuits and Systems (ISCAS), 05/2015.
"Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset", International Symposium on Quality Electronic Design, 03/2015.
"A 6.45 μW Self-Powered IoT SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios", ISSCC, San Francisco, CA, 02/2015.
"Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization", Transactions of Very Large Scale Integration Systems, 2015.
"Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems", International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.
"LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications", GOMAC Tech, 2014.
"Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories", VLSI Design Conference, 2014.
"A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs", S3S Conference, Monterey, CA, 10/2014.
"An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications", Journal of Low Power Electronics and Applications (JLPEA), vol. 4, issue 2, pp. 19, 05,2014.
"Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits", International Symposium on Quality Electronic Design (ISQED), 02,2014.
"A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs", International Symposium on Quality Electronic Design (ISQED), 02,2014.
"A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance", Journal of Solid State Circuits, 2014.
"Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM", Design Automation Conference (DAC), 2014.
"A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications", Symposium on VLSI Circuits, 2013.
"Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method", S3S Conference, Monterey, California, 10/2013.
"Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization", SRC TECHCON, 09/2013.
"A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers", Journal of Low Power Electronics and Applications, 05/2013.
"Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN", Design Automation and Test Europe, 03/2013.